AMD has provided further details on its Venice Epyc processors, marking its largest architectural shift in CPU design since 2019's Rome debut. The Zen 6-based product line is described as AMD's broadest CPU portfolio to date, covering general purpose, high-performance computing (HPC), artificial intelligence (AI), and future consumer platforms.
The Epyc 9006 SP7 platform will offer up to 256 cores, 16 channels of DDR5, and 128 lanes of CXL 3.1-compatible PCIe 6.0 connectivity. Venice will be available in two distinct versions: density-optimised and frequency-optimised. The 256-core variant is the density-optimised part, while a 96-core version capable of boosting to 5 GHz is also in development.
AMD's new chiplets double the number of compute cores to 32 and quadruple the shared L3 cache to 128 MB per chiplet, resulting in a gigabyte of L3 onboard for fully loaded Venice CPUs. The cache hierarchy has been updated, ensuring at least 4 MB of shared L3 per core, regardless of the core-complex die (CCD) type.
The new processors also feature two I/O dies, supporting 16 channels of DDR5 8000 MT/s or 12,800 MT/s memory using MRDIMMs. This provides up to 1.6 TB/s of memory bandwidth, which AMD states can achieve approximately 1.3 TB/s in STREAM Triad benchmarks.
For HPC-centric applications, AMD is reintroducing its Epyc X-chips with Venice-X parts, which will share the SP7 socket and push L3 cache per core to 12 MB or 1,152 MB per socket. These chips use 3D V-Cache packaging technology, stacking SRAM on top of CCDs to enhance cache capacity for workloads like computational fluid dynamics and electronic design automation.