US technology giant IBM has announced a significant leap forward in chip manufacturing, revealing a prototype chip that crams almost 100 billion transistors onto a fingernail-sized piece of silicon. This remarkable density, nearly twice that of existing leading chips, has been achieved through a pioneering three-dimensional stacking technique, which layers two silicon circuits on top of each other.
The company projects that this new 10mm by 15mm chip will deliver a 70 per cent improvement in energy efficiency and a 50 per cent boost in performance compared to today's most advanced chips. IBM anticipates that devices incorporating this technology could be available commercially within the next ten years, potentially transforming a wide array of electronic products.
For decades, chip manufacturing progress was measured by the shrinking size of individual transistors, expressed in nanometres. Smaller transistors generally meant higher density, faster computation, and lower energy consumption. However, this traditional metric has become increasingly complex, with 'nanometre' labels now often serving as marketing terms rather than precise physical measurements, according to Huiming Bu at IBM.
The true innovation behind IBM's latest development, which the company refers to as '0.7 nanometre' technology, lies not in the physical size of its components but in a sophisticated 15-year development process. This process allows for the seamless stacking of two silicon chip layers, creating all necessary electrical connections without overheating, and critically, being suitable for mass production. This marks a shift from traditional scaling along X and Y axes to introducing scaling in the Z-direction.
While precise details on component dimensions remain undisclosed, information released by IBM suggests this new technology essentially comprises two layers of the company's 2-nanometre chip, first announced in 2021. That earlier technology is already being manufactured by major foundries globally and is expected to feature in upcoming generations of devices, including the next Apple iPhone. Experts, such as Owen Guy from Swansea University, note that while other manufacturers claim high transistor densities, they often use multiple silicon layers separated by thick substrates, which hinders true 3D design and can create cooling challenges.
The drive for ever-smaller and more powerful components is now less about physically shrinking devices like laptops or smartphones, and more about enhancing energy efficiency and thermal management. These improvements are crucial for extending battery life in mobile devices and significantly reducing the substantial energy consumption of data centres, which have a growing environmental footprint.